1. Field of the Invention
This invention relates to a data processing system which has an address bus whose bus width is smaller than the number of bits of an address register of a central processing unit.
2. Description of the Prior Art
On account of the progress of semiconductor technology, there have now been fabricated microcomputers in which central processing units are each formed with a one-chip LSI. In such an LSI, the number of input/output pins is limited; for example, the number of address pins is usually limited to about sixteen. Further, there is a demand for the adoption of a virtual memory system in microcomputers.
Consider the case where a logical address of the virtual memory system is such as, for example, shown in FIG. 1A; that is; the 0th to 14th bits indicate a page number in virtual memory, and the 15th to 23rd bits an address in page, and the real memory capacity is, for instance, 128K bytes. In such case, referring to FIG. 1B, the 0th to 7th bits indicate a page number or a leading address of the page in real memory, and the 8th to 16th bits an address in page.
Where the number of address pins is 16, a central processing unit cannot at one time send out such a 24-bit logical address as shown in FIG. 1A. In the case of an ordinary data processing system which is not a virtual memory system, the central processing unit is required to transfer such a 17-bit real address, as is shown in FIG. 1B, to a main memory without address conversion. However, if the number of address pins is 16, as mentioned above, it is impossible to send out at one time the 17-bit real address.
In the prior art systems, 8-bit registers R.sub.1, R.sub.2 and R.sub.3 are provided in a central processing unit 1, as shown in FIG. 2, and, in the case of delivering a logical address, address information of the 0th to 15 th bits is first sent out on an address bus 4, and then address information of the 16th to 23rd bits is sent out on the address bus 4. In this case, the bus width of the address bus 4 is 16-bit.
The page number in virtual memory, comprising the 0th to 14th bits (of the address information which is totally delivered in two transmissions), is converted into a page number in real memory (0th to 7th bits in FIG. 1B) by means of a dynamic address conversion part 2 shown in FIG. 3. The page number of the real address is thus provided by the dynamic address conversion part 2, the 15th bit of the logical address page number being retained unconverted, and the address in page (15th to 23rd bits) being transferred subsequently. Then, a real address is formed, which real address is provided to a main memory (not shown in FIG. 3) for access thereto.
In an ordinary data processing system which is not a virtual memory system, such real address information of the 17-bit configuration shown in FIG. 1B is stored in the registers R.sub.1, R.sub.2 and R.sub.3 which make up an address register 1a. In this instance, the information is stored with the 16th bit lying at the right-most end. Referring to FIG. 3, the address information of the 0th to 8th bits is provided on the address bus 4 and stored in a register 3. Next, the address information of the 9th to 16th bits is provided on the address bus 4 to form, with the address information previously stored in the register 3, address information of a 17-bit configuration, and this address information is transferred to the main memory.
As described above, in the case of the address bus having a bus width (16 bits) smaller than the number of bits (24 bits) of the registers R.sub.1, R.sub.2 and R.sub.3, the address information is divided into two portions and transferred in two transmissions so as not to overlap each other. In the above example of the prior art, the address information transferred second is 8-bit in size, so that in the case of the 24-bit configuration the address information corresponding to the full bus width of 16 bits is transferred first, whereas in the case of the 17-bit configuration the 9-bit address information is transferred first.
It is also disclosed, for example, in U.S. Pat. No. 3,969,706, that address information or data is transmitted and received in two stages due to the limitation imposed on the number of input/output pins. In this case, the address information or data is usually transmitted and received half at a time.
In the case of a virtual memory system, address conversion of the high-order part of the logical address is required, but when the high-order bit part is larger than M/2 (where M is the number of bits of a logical address register and the size of the address bus is assumed to be M/2), the number of said bits necessary for the address conversion cannot be obtained unless and until the second or subsequently transferred address information is received, so that the access speed becomes low as a result. When the high-order bit part is smaller than M/2, the address conversion can be achieved immediately upon reception of the first transferred address information, but means are required for holding an unconverted one of the bits of the first transferred address information when the conversion result is combined with the remaining bits.
In an ordinary data processing system which is not a virtual memory system, a real address having a number of bits smaller than M is set in the low order positions of an address register. The number of bits of this real address is usually larger than M/2, so that in the system of the type transferring address information half at a time, as referred to above, it is necessary to retain some of the first transferred bits.